The MIC processor is used as a coprocessor, similarly to a GPGPU.  It is effectively the Larrabee architecture: "Design elements inherited from the Larrabee project include x86 ISA, 512-bit SIMD units, coherent L2 cache, and ultra-wide ring bus connecting processors and memory."

The hardware maintains cache coherency across the cores, and presents a programming model that is the same as a multi-core Xeon.  Except, the cores are in-order, and have 512 bit vector units attached, and the communication times for cache misses are quite different.

More at:
[[http://www.many-core.group.cam.ac.uk/ukgpucc2/talks/Elgar.pdf | Architecture overview]]
[[http://en.wikipedia.org/wiki/Intel_MIC | MIC wikipedia]]